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International Journal of Reconfigurable and Embedded Systems (IJRES)

IJRES
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Published by Institute of Advanced Engineering and Science

ISSN : 20894864 EISSN : 27222608 DOI : -

Core Subject : Economy,

Economics, Econometrics & Finance

The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.

Arjuna Subject : -

Articles 7 Documents

Search results for , issue "Vol 6, No 1: March 2017" : 7 Documents clear

Android Based Switch Controlling Technique for LED Bulbs Using Bluetooth/Wi-Fi Technology Munigoti Saikiran; Lalith Nagaram Nagarajan; Malladi Bharath
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 6, No 1: March 2017
Publisher : Institute of Advanced Engineering and Science

This paper presents an efficient approach to switch on/off and control the intensity of an LED bulb from a remote place using Android Applications installed in a Smartphone. As LED household bulbs and lights are energy efficient, drop-in replacements for the incandescent lighting found in homes and offices. These lights produce a warm brightness while providing a significant cost savings over traditional lighting. Bluetooth & Wi-Fi modules are used simultaneously as an interface that make connection between Android Application and the LPC2148 controller by which the generated output can be viewed with the help of an LED bulb and control various other devices, based on the availability in particular areas.

FPGA based Implementation of Symmetrical Reduced Switch Multilevel Inverter K. Venkataramanan; B. Shanthi; T. S. Sivakumaran
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 6, No 1: March 2017
Publisher : Institute of Advanced Engineering and Science

Multilevel inverter has become more popular and attractive for drive applications. Among the various modulation techniques, Carrier based techniques has been commonly used because of their simplicity and flexibility. This paper presents the comparisons of bipolar multicarrier pulse width modulation for the new symmetrical multilevel inverter. The performance parameters of new multilevel inverter were analyzed through various switching strategies. The detailed study has been carried out by MATLAB/SIMULINK. The real time implementation was carried out using FPGA. The results of both simulation and experimentation were compared.

Implementation of High Speed Vedic Multiplier Using Vertical and Crosswise Algorithm G. Vadiraj; K. Shivanand; B. Sampat; G. Subramanya Nayak
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 6, No 1: March 2017
Publisher : Institute of Advanced Engineering and Science

Multiplication is an important fundamental function in arithmetic operations. Multiplication-based operations such as Multiply and Accumulate (MAC) and inner product are some of the frequently used operations in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform(FFT), filtering and in microprocessors in its arithmetic and logic unit. Since multiplication dominates the execution time of most DSP algorithms, so there is a need of high speed multiplier. Higher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing applications. In this project, the comparative study of Vedic multiplier and Sequential multiplier is done for low power requirement and high speed. The proposed architecture is based on the Vertical and Crosswise algorithm of ancient Indian Vedic Mathematics, which increases the speed of multiplier by reducing the number of clock cycles thus achieving the greater speed of the processor or system.

FPGA Based Symmetrical Multi Level Inverter with Reduced Gate Driver Circuits G. Durga Prasad; V Jegathesan
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 6, No 1: March 2017
Publisher : Institute of Advanced Engineering and Science

Multilevel converters tender advantages in terms of the output waveform quality due to the increased number of levels used in the output voltage modulation and have been widely accepted for high-power high-voltage applications. This paper introduces topology in multilevel dc link inverter (MLDCLI), which can significantly reduce the switch count and improve the performance. The preferred topology provides a dc voltage with the shape of a staircase approximating the rectified shape of a commanded sinusoidal wave, to the bridge inverter, which in turn gives the required alternating waveform. This topology requires fewer components compared to traditional Multi level Inverters (MLI).Therefore, the overall cost and complexity are significantly reduced particularly for higher output voltage levels. Finally, Matlab/Simulink and XILINX are used as a simulation and compiler architecture of control circuit embedded in FPGA. Simulation and experimental results for fifteen-level inverter are presented for validation.

On-chip AMBA Bus Based Efficient Bridge between High Performance and Low Peripheral Devices Anurag Shrivastava; Sudhir Kumar Sharma
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 6, No 1: March 2017
Publisher : Institute of Advanced Engineering and Science

Today’s scenario of SOC deals with integrity and sharing of information or data with various level of communication. AMBA bus protocol has been proposed by ARM community to justify the uneven demand of integrity .In this paper functional description and implementation of high peripheral devices supporting protocol AXI2.0 and its interface between low peripheral devices has been proposed. The connection named as bridge take care of the protocol mismatch and operates on data transfer for uneven speed demand. Asynchronous FIFO has been considered to avoid the complex handshaking mechanism. The design has been implemented within VHDL and implemented on Xilinx Virtex 4.

Simulation and Real Time Implementation of Various PWM Strategies for 3 Φ Multilevel Inverter Using FPGA C. R. Balamurugan; S. P. Natarajan; T. S. Anandhi; B. Shanthi
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 6, No 1: March 2017
Publisher : Institute of Advanced Engineering and Science

For high power applications Multilevel Inverter (MLI) is extensively used. The major advantages of MLI are good power quality, low switching losses and maintenance of the desired voltage. In this work, the three phase cascaded multi level inverter is analyzed under various modulation techniques that include Sub-Harmonic Pulse Width Modulation (SHPWM) i.e. Phase Disposition (PD) strategy, Phase Opposition Disposition (POD) strategy, Alternate Phase Opposition Disposition (APOD) strategy, hybrid strategy (PD and PS) and Phase Shift (PS) strategy. The study will help to choose those techniques with reduced harmonics for the chosen three phase cascaded MLI with R-L load. The Total Harmonic Distortion (THD), VRMS (fundamental), crest factor and form factor are evaluated for various modulation indices at two different switching frequencies (3.15KHz and 6 KHz). Simulation is performed using MATLAB-SIMULINK. It is observed that HYBRID PWM and PSPWM methods provide output with relatively low distortion for low and high switching frequencies. PODPWM and PSPWM are found to perform better since they provide relatively higher fundamental RMS output voltage for 6 KHz and 3.15 KHz switching frequencies. The experimental result shows PSPWM provide output with low distortion and HYBRID PWM provide output with higher fundamental RMS voltage for fc=3.15KHz. The experimental results were obtained only for fc=3.15KHz.

FPGA-based Architecture of Direct Torque Control Azaza Maher; Echaieb Kamel; Mami Abdelkader
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 6, No 1: March 2017
Publisher : Institute of Advanced Engineering and Science

This paper presents an optimized FPGA architecture of a DTC “direct torque control” drive of an induction motor. The proposed architecture is based on variable fixed point world size and the use ipcores in order to achieve higher sampling frequency which leads to reduce the electromagnetic torque and flux ripples. The hardware implementation was experimentally validated, the results shows the effectiveness of the hardware DTC drive implementation by the minimization of the torque and flux ripple

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